IC Verification, SystemVerilog and UVM Course
The course will tackle pre-ASIC development of RLT (real-time logic) design and verification using SystemVerilog and UVM. The course will require Cadence / Synopsys simulation tools in order to simulate and test RTL design. Students will learn a knowledge of basic NAND/ NOR gate knowledge and digital design for chips via this course.
Course DetailsWho Should Attend: Engineers, Designers, Beginners
Program information: This is a basic level, Instructor-led course delivered through in-classroom lectures, hands-on lab training, extensive class notes and Certification. Courses are taught by semiconductor industry experienced professionals. Free job consultation provided.